1. Field of the Invention
The present invention relates to use the differential current to proceed write operation on the circuit of SRAM that is different with the general write operation by using differential voltage. There is one more transistor in the new SRAM's memory cell than that in the conventional memory cell in which there are six transistors. The extra equalization transistor equalize the electric potential in the memory cell in advance, and then the differential current of input data is transmitted to memory cell through the current conveyor. In addition, the differential current going into the memory cell will be amplified by the strong positive feedback of the memory cell to pull out the differential voltage.
2. The Description of the Prior Art
In the past, the development of SRAM circuit is mainly using the different voltage-mode sense amplifier to increase the read-operation speed of the memory, as shown in Attachment 1. In the past few years, the related publications of current-mode SRAM utilized the current-mode read-operation as shown in Attachment 2. The current-mode read-operation can reduce the swing of bit-line, and it can not only increase the read speed, but also reduce the power loss of the bit-line which is usually loaded with large capacitance. Of course, it also reduces the power loss of entire memory. Although there is a current-mode read circuit, the data writing still depends on the voltage-mode circuit. The voltage mode write-operation should pull back the bit-lines to power supply V.sub.dd, and the swing is almost equal to the power supply voltage (V.sub.dd) in order to destroy and renew the original data in the memory cell. As it requires very large potential swing, there is large power loss when write the data into the memory, and also prolongs the memory cycle time. As the whole cycle time is the sum of one writing cycle time plus one reading cycle time, the operating speed of a general SRAM is not only limited by the reading time, but also limited by the cycle time.